Product Features Datasheet Enhanced IP Protocol Support — TCP, UDP, IPv4 checksum offload — Received checksum verification Quality of Service (QoS) — Multiple priority transmit queues Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — 32-bit PCI master interface 2 — Thin BGA 15mm package Integrated power management functions — ACPI and PCI power management standards compliance — Wake on “interesting” packets and link status change support PHY detects polarity, MDI-X, and cable lengths. Auto MDI, MDI-X crossover at all speeds XOR tree mode support High Performance Networking Functions — Early release — 8255x controller family chained memory structure — Improved dynamic transmit chaining with multiple priorities transmit queues — Full pin compatibility with the 82559 and 82559ER controllers — Backward compatible software to 82559ER controllers — Full duplex support at 10 and 100 Mbps — IEEE 802.3u auto-negotiation support — 3 KB transmit and receive FIFOs — Fast back-to-back transmission support with minimum interframe spacing — IEEE 802.3x 100BASE-TX flow control support — Adaptive Technology Low Power Features — Advanced Power Management (APM) capabilities — Low power 3.3 V device — Efficient dynamic standby mode — Deep power-down support — Clockrun protocol support 82551ER Enhancements — Improved bit error rate performance — HWI support — Deep power-down state power reduction 1 Lead-free 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx. 1 This device is lead-free. That is, lead has impurity at <1000 ppm. The Material concentration of other Restriction on In addition, this device has been tested and versions of the device. For more information regarding lead-free representative. not been intentionally added, but lead may still exist as an Declaration Data Sheet, which includes lead impurity levels and the Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks conforms to the same parametric specifications as previous products from Intel Corporation, contact your Intel Field Sales 317802-005 Revision 3.1 Revision History Revision Date Jan 2002 Apr 2002 Mar 2003 Sep 2004 Nov 2004 Nov 2004 Jan 2005 Oct 2006 Sept 2007 Sept 2007 Mar 2008 Sept 2008 Nov 2008 Revision 1.0 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 Description • Added description for No Connect pins and corrected typographical errors. • Clarified EEPROM address map and word definitions for the 82551ER. • Added more detailed information for I in the DC specifications table. CC Changed document status to Intel Confidential. • Removed document status. • Removed references to MDI/MDI-X feature, not supported by the 82551ER. • Added references to the MDI/MDI-X feature. • Added lead-free information. • Removed EEPROM Map bit descriptions. These descriptions can now be found in the 82551QM/ER/IT EEPROM Map and Programming Information. • Added 82551ER Test Port Functionality (Chapter 10). • Added new values for RBIAS100 and RBIAS10. RBIAS100 = 649 and RBIAS10 = 619 . • Removed all references to the Read the full 82551ER Fast Ethernet PCI Controller Networking Silicon - 82551ER.