Datasheet: Intel® 5100 Memory Controller Hub Chipset.
The Intel® 5100 Memory Controller Hub Chipset is designed for systems based on Intel® Xeon® processor 5100 and 5300 series , Intel® Xeon® processor 5200 and 5400 series, and Intel® Core™2 Duo Processor T9400.
Intel® 5100 Memory Controller Hub chipset device and documentation errata, specification clarifications, and changes.
This document is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating systems, and tools.
Specification Update, 2009: Intel® 5400 Express Chipset memory controller hub (MCH), clarifications, changes, and documentation errata.
Specification updates for the Intel® 5400 Express Chipset Memory Controller Hub (MCH), including device and documentation errata, specification clarification, and changes.
The Intel® 5520 and 5500 Chipset I/O Hub components provide a connection point between various I/O components and Intel® QuickPath Interconnect based processors. The Intel® 5520 and 5500 Chipsets are combined with Intel® Xeon® Processor 5500 Series.
Application Note: Interrupt swizzling solution for Intel® 5000 series chipset-based platforms.
Details the interrupt swizzling scheme and the programming and implementation requirements for the Intel® 5000 series chipset.
Guide: Solution architecture of a private cloud based on OpenStack*. Includes several enhancements to security and energy efficiency.
Guide: Solution architecture of a private cloud based on OpenStack*. Includes several enhancements to security and energy efficiency that take advantage of Intel processor architecture, advanced technologies, and software components.