caltiming8

         
      
Module Instance Base Address Register Address
i_io48_hmc_mmr_io48_mmr 0xFFCFA000 0xFFCFA09C

Offset: 0x9C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_mmr_cmd_to_valid

0x0

cfg_t_param_rld3_multibank_ref_delay

0x0

cfg_t_param_mps_exit_cke_to_cs

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_mps_exit_cke_to_cs

0x0

cfg_t_param_mps_exit_cs_to_cke

0x0

cfg_t_param_mpr_to_valid

0x0

cfg_t_param_mrr_to_valid

0x0

caltiming8 Fields

Bit Name Description Access Reset
27:20 cfg_t_param_mmr_cmd_to_valid
MMR cmd to valid delay
RW 0x0
19:17 cfg_t_param_rld3_multibank_ref_delay
RLD3 Refresh to Refresh Delay for all sequences
RW 0x0
16:13 cfg_t_param_mps_exit_cke_to_cs
Timing parameter for exit Maximum Power Saving. Timing requirement for CKE de-assertion vs CS de-assertion. tMPX_LH
RW 0x0
12:9 cfg_t_param_mps_exit_cs_to_cke
Timing parameter for exit Maximum Power Saving. Timing requirement for CS assertion vs CKE de-assertion. tMPX_S
RW 0x0
8:4 cfg_t_param_mpr_to_valid
Timing parameter for Multi Purpose Register Read to any valid command
RW 0x0
3:0 cfg_t_param_mrr_to_valid
Timing parameter for Mode Register Read to any valid command
RW 0x0