Control Register 1
This register exists only when the DW_apb_ssi is configured as a
master device. When the DW_apb_ssi is configured as a serial slave,
writing to this location has no effect; reading from this location
returns 0. Control register 1 controls the end of serial transfers
when in receive-only mode. It is impossible to write to this
register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled
and disabled by writing to the SSIENR register.
Module Instance | Base Address | Register Address |
---|---|---|
i_spim_0_spim | 0xFFDA4000 | 0xFFDA4004 |
i_spim_1_spim | 0xFFDA5000 | 0xFFDA5004 |
Offset: 0x4
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ndf RW 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
15:0 | ndf | Number of Data Frames. When TMOD = 10 or TMOD = 11, this register field sets the number of data frames to be continuously received by the DW_apb_ssi. The DW_apb_ssi continues to receive serial data until the number of data frames received is equal to this register value plus 1, which enables you to receive up to 64 KB of data in a continuous transfer. When the DW_apb_ssi is configured as a serial slave, the transfer continues for as long as the slave is selected. Therefore, this register serves no purpose and is not present when the DW_apb_ssi is configured as a serial slave. |
RW | 0x0 |