Intel® FPGA Complete SerialLite II Solution

Table 1. Complete SerialLite II Solution



Device Family

Physical Interface

Integrated PHY providing full PMA (1) and PCS (2) support

SerialLite II IP Core

Intel FPGA SerialLite II IP Core ›

Development Board

Characterization Report

Stratix II GX Characterization Report
Contact your local sales representative ›

Reference Design

SerialLite II Loopback Reference Design, available with IP

Table 2. Features and Benefits of SerialLite II




Data Flow

Full-duplex, simplex, asymmetric, or broadcast

Reduced logic for simplex, asymmetric, or broadcast applications

Data Type

Packet or streaming

Support for a variety of applications

Link Width

1 to 16 lanes

Scalable link throughput from 622 Mbps to 102 Gbps in each direction

Lane Rate

622 Mbps to 6.375 Gbps

Datapath Width

8 bits, 16 bits, or 32 bits
(per lane)

Reduced logic for lane rates below 1.5 Gbps and scalability to 6.375-Gbps lane rates



Industry-standard encoding for the most reliable clock and data recovery


Payload and idle, or none

Reduced EMI for high lane rates

Reference Clock

Asynchronous or synchronous

Suitable for chip-to-chip, board-to-board, and backplane applications

Polarity Reversal

Yes or no

Implement the functionality required for your specific application for a cost-optimized solution

Data Integrity Protection

CRC-32, CRC-16, or none

Packet Type

Data, priority, or both

Optional logic to insert high-priority data or control information

Flow Control

Data packet, priority packet, both, or none

Implement the functionality required for your specific application for a cost-optimized solution


Priority packet or none

Increased link reliability

Channel Multiplexing

Yes or no

Support for applications with multiple logical channels

Atlantic Interface

Data and priority ports

Well-defined interface to user logic and a variety of Intel FPGA IP functions to accelerate design cycles for unique bridging solutions