Intel FPGAs provide the flexibility, performance, and scalability needed for cost-effective 5G solutions.
Compared to its predecessors, 5G is more than just another generational leap - it is the foundation for universally connected digital society. This demands a series of superlatives: 100x typical end user data rate; 100x number of connected devices; and 1,000x higher mobile data volume - all the while connecting to a more diverse set of end-user applications. To meet these requirements, 5G is looking to employ existing and potentially new RAT's, utilize new technologies such as Massive MIMO along with new deployment scenarios like cloud-based RAN, yet still remain a cost-effective solution for practical implementation.
A likely deployment scenario for 5G is a cloud-based radio access network, or C-RAN, that employs a centralized datacenter-like architecture for baseband processing of a larger number of remote radio heads. Intel FPGAs are vital for this approach, as they can be used with Xeon processors for hardware acceleration and virtualized functionalities.
But while the demands of 5G are sure to be enormous, the specific technologies that will be used to meet these demands still remain uncertain. Intel programmable FPGA's and solutions offer the necessary flexibility and performance needed to meet the ambitious and ever-changing demands of 5G wireless connectivity.
With the Internet of Things approaching, the number of wireless connected devices is set to explode, and a diverse set of connectivity types will be needed for a significantly larger amount of diverse applications. Because of this, 5G will require:
As of now, there are a myriad of proposed solutions and technologies to meet the challenges of 5G and not only facilitate a universally connected society, but to achieve it with cost effective solutions. These include:
However, it is uncertain which combination of these technologies will provide the most complete and cost-effective solution for the demands of 5G. It is vital that wireless infrastructure achieve the right balance of flexibility and performance in order to keep up with the changing and increasing demands of the wireless market.
Intel offers high-end, mid-range, and low-cost devices that can be tailored to fit individual business needs for 5G implementation. Intel's 5G solution provides:
Intel provides optimized solutions for the following 5G technologies
The Centralized/Cloud Radio Access Network (C-RAN) has attracted tremendous attention from the wireless infrastructure industry in the recent years. This is due to the substantial benefits introduced by the C-RAN architecture including lower total-cost-of-ownership (TCO), enhanced spectral efficiency, and simplified support of multi-standards and future evolution. Perhaps more importantly, this architecture complements the industry’s migration toward Network Functionality Virtualization (NFV) and Self Organized Networks (SON) in terms of network architecture convergence.
The ever-increasing use of smart phones and other portable devices is driving exponential growth in mobile broadband data traffic and capacity demands. This presents significant challenges to the existing wireless network:
Due to these limitations in the existing wireless network, the industry is trying to optimize the network architecture by considering a number of key innovations. Together these enhancements are termed C-RAN.
Driven by these architectural innovations, C-RAN solutions have the potential to introduce tremendous inherited advantages by physically aggregating BTS processing to a single site.
Full Centralized Architecture
Figure 1 illustrates the fundamental rationale of the C-RAN with full centralization. The Remote Radio Unit (RRU) sites stay the same as the conventional radio networks, while the Baseband Unit (BBU) moves from being co-located with the RRU to a centralized location. The BBU includes Physical Layer (L1) and higher layer functions, mapped onto a large pool of processing resources that accomplish the virtualized NodeB functionalities.
In order to connect multiple traffic streams together in a dynamic fashion, a switch layer called cloud terminator is also introduced. This layer is used to bridge, connect, and control different interface protocols to facilitate dynamic load balancing.
LTE places very strict latency requirements on data processing. For example, round trip latency must be < 5 ms and baseband frame processing must be < 1 ms. As a consequence, the transmission between the RRU sites and the centralized BBU site must be high throughput (≥10Gbps) and requires latency as low as tens of microseconds.
FPGAs Are a Keystone of CRAN Architecture
The key requirements of CRAN are reconfigurability, low and deterministic latency operation, flexible HW accelerators and high speed switching performance which make FPGAs a natural component of any CRAN architecture.
The cellular infrastructure known as the Radio Access Network (RAN) has been evolving since the first analog FM cellular solution (first generation or 1G) in the 1980s. During this evolution, the Radio Access Technology (RAT) moved from GSM to LTE and the network topology changed from circuit-switched (TDM) to packet-switched (IP) with continual reduction in latency, improved throughput, spectral efficiency, and peak speeds. These changes translated into a new infrastructure that is faster, smarter, and more elastic in its use of resources. This transition requires more processing power and intelligence in the Basestation or eNodeB.
The basestation is now evolving to a super-intelligent wireless router. Specifically, the basestation, or eNodeB, now processes the entire PHY, MAC, Radio Link Control (RLC), Packet Data Convergence Protocol (PDCP), and Radio Resource Control (RRC) for multiple interface standards, at 10 times the data throughput.
These advancements result in a “soft/flexible” basestation supporting multiple standards at the right price. Furthermore, basestation solutions must scale from picocells, to microcells, and to macrocells.
OEMs’ desire to re-use their basestation chassis, the high processing requirements for next-generation basestation architectures, and the need to reduce overall system latency and address both flexibility and scalability are all driving the need for highly integrated system on a chip (SoC) solutions with both hardware and software flexibility for interfaces and processing with inherent scalability. The figure above illustrates typical macro basestation architecture.
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