Introduction
Development Kit
| IP Core | IP Core Category |
|---|---|
| Altera In-System Sources & Probes | SimulationDebugVerification |
| Reset Controller | QsysInterconnect |
| MM Interconnect | QsysInterconnect |
| Avalon-MM Master Translator | QsysInterconnect |
| Avalon-MM Slave Translator | QsysInterconnect |
| altera_jtag_avalon_master | QsysInterconnect |
| Avalon-ST Packets to Bytes Converter | QsysInterconnect |
| Avalon-ST Timing Adapter | QsysInterconnect |
| Avalon Packets to Transaction Converter | QsysInterconnect |
| Avalon-ST Single Clock FIFO | QsysInterconnect |
| Avalon-ST Channel Adapter | QsysInterconnect |
| Avalon-ST Bytes to Packets Converter | QsysInterconnect |
| Avalon-ST JTAG Interface | QsysInterconnect |
| altera_config_stream_endpoint | Debug & Performance |
| Top level generated instrumentation fabric | Debug & Performance |
| Altera SDM Mbox Bridge | Configuration and Programming |
| Altera SDM IRQ | Configuration and Programming |
| Altera SDM2FPGA Bridge | Configuration and Programming |
| Altera SDM GPO | Configuration and Programming |
| Altera SDM GPI | Configuration and Programming |
| Altera FPGA2SDM Bridge | Configuration and Programming |
| Memory-Mapped Multiplexer | QsysInterconnect |
| Avalon-ST Handshake Clock Crosser | QsysInterconnect |
Detailed Description
The Mailbox Client Intel FPGA IP is a bridge between a host and the Secure Device Manager (SDM) You use the Mailbox Client Intel FPGA IP to send commands and receive status from SDM peripheral clients. The Mailbox Client Intel FPGA IP is an Avalon® memory-mapped (Avalon-MM) slave component that must connect to an Avalon-MM master.
In this reference design, the JTAG-to-Avalon Master acts as the host controller connecting to the Mailbox Client Intel FPGA IP core. The JTAG-to-Avalon Master Bridge IP translates the commands it receives from the System Console to an Avalon-MM format that the Mailbox Client Intel FPGA IP core requires. Mailbox Client Intel FPGA IP: drives commands and receives responses from the SDM.
The rsu1.tcl script provides examples to perform the available command functions supported by SDM. You can run the functions available in the rsu1.tcl script via System Console of the Intel Quartus® Prime software to perform the following operations,
- Read FPGA IDCODE
- Read FPGA CHIP ID
- QPSI flash access operations such as program QSPI flash with .rpd file.
- Remote System Update (RSU) operations such as reading RSU status and trigger reconfiguration from the data source which can be either an application image or factory image.
Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
Prepare the design template in the Quartus Prime software command-line
At the command-line, type the following command:
quartus_sh --platform_install -package <project directory>/<project>.par
Once the process completes, then type:
quartus_sh --platform -name <project>