F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

ID 709308
Date 11/03/2023
Public
Document Table of Contents

1.3. Generating the Design

Use the DisplayPort Intel® FPGA IP parameter editor in Intel® Quartus® Prime software to generate the design example.
Figure 3. Generating the Design Flow
  1. Select Tools > IP Catalog, and select Intel Agilex® 7 F-Tile as the target device family.
    Note: The design example only supports Intel Agilex® 7 F-Tile devices.
  2. In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP. The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  4. Select an Intel Agilex® 7 F-Tile device in the Device field, or keep the default Intel® Quartus® Prime software device selection.
  5. Click OK. The parameter editor appears.
  6. Configure the desired parameters for both TX and RX.
    Note: The Nios® II software has the capability to read and print out the DisplayPort Main Stream Attribute (MSA) information in the Nios® II terminal. To read or print the MSA information, turn on the Enable GPU Control parameter.
  7. Under the Design Example tab, select DisplayPort SST Parallel Loopback Without PCR, DisplayPort SST Parallel Loopback with AXIS Video Interface, DisplayPort SST TX-only, or DisplayPort SST RX-only.
  8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example. You must select at least one of these options to generate the design example files. If you select both, the generation time becomes longer.
  9. For Target Development Kit, select Intel Agilex® 7 I-Series SoC Development Kit. This causes the target device selected in step 4 to change to match the device on the development kit. For Intel Agilex® 7 I-Series SoC Development Kit, the default device is AGIB027R31B1E1VAA.
  10. Click Generate Example Design.