Arria® V FPGA and SoC FPGA

The Arria® V FPGA family offers the highest bandwidth and delivers the lowest total power for midrange applications, such as remote radio units, 10G/40G line cards, and broadcast studio equipment. There are five targeted variants, including SoC variants with a dual-core ARM* Cortex*-A9 hard processor system (HPS) to best meet your performance, power, and integration needs.

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Arria® V FPGA and SoC FPGA

Device All Arria® V SoC FPGA Devices (SX, ST)

Dual-core ARM* Cortex*-A9 MPCore* processor with ARM* CoreSight* debug and trace technology

  • 1.05 GHz CPU clock rate in -I3 speed grade
  • 925 MHz CPU clock rate in -C4 speed grade
  • 800 MHz CPU clock rate in -C5, -I5 speed grades
  • 700 MHz CPU clock rate in -C6 speed grade
Coprocessors ARM* NEON* media processing engine with Vector Floating-Point (VFP) v3 double-precision floating point unit for each processor, Snoop Control Unit (SCU), Acceleration Coherency Port (ACP)
Level 1 cache 32 KB L1 instruction cache, 32 KB L1 data cache
Level 2 cache 512 KB shared L2 cache
On-chip memory 64 KB on-chip RAM, 64 KB on-chip ROM
HPS hard memory controller

Multiport SDRAM controller with support for DDR2, DDR3, DDR3L, and LPDDR2 with optional error correction code (ECC) support
533 MHz/1066 Mbps external memory interface
User-configurable memory width of 8, 16, 16+ECC, 32, 32+EEC
Up to 4 GB address range, with built-in memory protection control

Quad serial peripheral interface (SPI) flash controller Supports SPIx1, SPIx2, or SPIx4 (quad SPI) serial NOR flash devices
Up to four chip selects
SD/SDIO/MMC controller

Supports SD, eSD, SDIO, eSDIO, MMC, eMMC, and CE-ATA with integrated DMA

NAND flash controller Supports 8 bit ONFI 1.0 NAND flash devices
Programmable hardware ECC for Single-Level Cell (SLC) and Multi-Level Cell (MLC) devices
Ethernet media access controller (EMAC) 2 x 10/100/1000 EMAC with RGMII external PHY interface and integrated DMA
USB On-The-Go controller (OTG) 2 x USB 2.0 OTG controllers with ULPI external PHY interface and integrated DMA
UART controller 2 x UART 16550 compatible
SPI controller 2 x SPI masters
2 x SPI slaves
I2C controller 4 x I2C
General-purpose I/O (GPIO) Up to 71 GPIO and 14 input-only pins, with digital de-bounce and configurable interrupt mode
Direct memory access (DMA) controller 8-channel direct memory access (DMA)
Supports flow control with 31 peripheral handshake interfaces
Timers Private interval and watchdog timer for each processor
Global timer for processor subsystem
4X general-purpose timers
2X watchdog timers
Maximum HPS I/O 208
HPS phased-locked loops (PLLs) 3