Arria® V FPGA and SoC FPGA

The Arria® V FPGA family offers the highest bandwidth and delivers the lowest total power for midrange applications, such as remote radio units, 10G/40G line cards, and broadcast studio equipment. There are five targeted variants, including SoC variants with a dual-core ARM* Cortex*-A9 hard processor system (HPS) to best meet your performance, power, and integration needs.

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Arria® V FPGA and SoC FPGA

Feature Arria® V GZ FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V ST SoC Arria® V SX SoC
ALMs (K) 170 190 190 174 174
Variable-Precision DSP 1,139 1,156 1,156 1,068 1,068
M20K Blocks 1,700 - - - -
M10K Blocks - 2,414 2,414 2,282 2,282
DDR3 Memory Interface Speed 800 MHz 667 MHz 667 MHz 667 MHz 667 MHz
Hard Memory Controllers - 4 4 4 4
Transceivers (Gbps) 12.5 Gbps 10.3125 6.5536 10.3125 6.5536
PCI Express® (PCIe*) Gen3/2/1 hardened IP block 1 - - - -
PCIe* Gen2/1 hardened IP blocks(s) - 2 2 2 2
Design Security x x x x x
Single Event Upset (SEU) Mitigation x x x x x

Features Arria® V GZ Arria® V GT Arria® V GX
Maximum number of transceivers 36 36 36
12.5 Gbps backplane capable transceivers x - -
10.3125 Gbps transceivers for SFF-8431 applications x x -
6.375 backplane capable transceivers x x x
Continuous-time linear equalization - Receiver 4-stage linear equalization x - -
Decision feedback equalization - Receiver 5-tap digital equalizer x - -
Adaptive equalization - Automatically adjust equalization x - -
Linear equalizer - x x
Transmit equalization pre-emphasis (4-Tap) x - -
Transmit equalization pre-emphasis (3-Tap) - x x
Ring oscillator transmit PLLs x x x
LC oscillator PLLs x - -
On-die instrumentation (EyeQ data-eye monitor) x - -

Arria® V and Cyclone® V FPGA Multipliers in Single-Block Mode

Number of Multipliers

Multiplier Precision

Three independent multipliers

9x9

Two multipliers in sum mode

18x19

Two independent multipliers

18x19

One independent asymmetric multiplier

18x36 (requires additional logic outside the DSP block)

One independent high-precision multiplier

27x27

Arria® V and Cyclone® V FPGA Multipliers in Multiple-Block Mode

Type of Multipliers

Number of Blocks Required

One independent 36x36 multiplier

2 (requires additional logic outside the DSP block)

One independent 54x54 multiplier

4 (requires additional logic outside the DSP block)

One 18x18 complex multiplier

2

One 18x25 complex multiplier

4 (requires additional logic outside the DSP block)

One 18x36 complex multiplier

4 (requires additional logic outside the DSP block)

One 27x27 complex multiplier

4

Cascade Bus

All modes feature a 64-bit accumulator and each variable-precision DSP block comes with a 64-bit cascade bus that allows implementation of even higher precision signal processing by cascading multiple blocks using a dedicated bus.

The variable-precision DSP architecture maintains backward compatibility. It can efficiently support existing 18-bit DSP applications, such as high-definition video processing, digital up or down conversion, and multi-rate filtering.

Device Package Speed Grade
Arria® V GZ F780, F1152, F1517 C3, C4, I3L, I4
Arria® V SX/GX/ST/GT F672, F896, F1152, F1517 C4, C5, C6, I3, I5