Cyclone® IV FPGA

Complete Design Resources

For a smooth and successful design flow that quickly turn your ideas into revenue, Intel provides a complete Cyclone® IV FPGA design environment including:

• Intel® Quartus® Prime development software
• Library of proven IP
• Nios® II, the world's most versatile embedded processor

Cyclone® IV GX FPGAs: Transceiver Overview

The Cyclone® IV FPGA family extends the Intel® Cyclone® FPGA series leadership in providing the market’s lowest cost, lowest power FPGAs, now with transceivers.

Not all low-cost transceivers are created equally. The Cyclone® IV GX FPGA was specifically designed to allow the implementation of multiple protocols in a single quad and to allow independent receive and transmit frequencies. This flexibility helps you fully utilize all available transceiver resources and keep designs in a smaller and lower cost device.

Key Transceiver Features:

• Up to eight transceivers with clock data recovery (CDR), supporting data rates from 600 Mbps to 3.125 Gbps.
• Flexible and easy-to-configure transceiver datapath to implement industry-standard and proprietary protocols.
• Programmable pre-emphasis settings and adjustable differential output voltage (VOD) for improved signal integrity.
• User-controlled receiver equalization to compensate for frequency-dependent losses in the physical medium.
• Dynamic reconfiguration of the transceiver to support multiple protocols and data rates on the same channel without reprogramming the FPGA.
• Support for protocol features such as spread-spectrum clocking in PCI Express*, DisplayPort, V-by-One, and SATA configurations.
• Dedicated circuitry compliant with the physical interface for PCI Express*, XAUI, and Gbps Ethernet.
• PIPE interface that connects directly to embedded PCI Express* Gen1 (2.5 Gbps) hard intellectual property (IP) to support PCI-SIG* compliant x1, x2, or x4. endpoint or rootport applications.
• Two phase-locked loop (PLL) inputs on each transmitter; the EP4CGX50 device and larger devices also have independent clock dividers to allow different clock rates for each channel.
• Built-in byte ordering so that a frame or packet always starts in a known byte lane.
• 8B/10B encoder and decoder that performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding.
• On-die power supply regulators for transmitter and receiver PLL charge pump and voltage controlled oscillator (VCO) for superior noise immunity.
• On-chip power supply decoupling to satisfy transient current requirements at higher frequencies, which reduces the need for on-board decoupling capacitors.
• Diagnostic features such as serial loopback, parallel loopback, reverse serial loopback, and loopback master and slave capability in the PCI-SIG* compliant PCI Express* hard IP block.

The following figure shows the block diagram of the Cyclone® IV GX FPGA transceivers, both physical medium attachment (PMA) and physical coding sublayer (PCS). The blocks within the PCS can be bypassed, depending on your requirements.

Cyclone® IV GX Transceivers, PMA & PCS Block Diagram