Intel® Quartus® Prime Software

The intuitive high-performance design environment.

Quick-Start for Intel® Quartus® Prime Pro Edition Software

Intel® Quartus® Prime Pro Edition User Guide: Getting Started

Download Intel® Quartus® Prime Software Brochure

Intel® Quartus® Prime Software

Intel Agilex® Device Support

The Intel® Quartus® Prime Pro Edition Software v23.1 supports the Intel Agilex® device families, including the latest Intel Agilex® 7 FPGA M-Series devices. The Intel Agilex® 7 FPGA family leverages the full breadth of Intel innovation and manufacturing capability. Built with advanced 10 nm SuperFin technology (F-Series and I-Series), Intel 7 technology (M-Series), and a second-generation Intel® Hyperflex™ FPGA Architecture, Intel Agilex® 7 devices deliver ~2X better fabric performance per watt1 compared to competing 7 nm FPGAs. They also offer integrated Arm-based processors, transceivers up to 116Gbps, PCI Express (PCIe) 5.0, and Compute Express Link (CXL). These features make them ideal for a wide range of applications in many markets including data center, networking, broadcast, defense, and industrial.

Design Netlist Infrastructure Customer Feedback Beta

Design Netlist Infrastructure

The Design Netlist Infrastructure (DNI) project is rapidly approaching broad release. With the Quartus Prime Pro Edition v23.1 release, DNI will be available as a “Customer Feedback Beta” release, allowing customers to try out the end-to-end DNI flow, the new RTL Analyzer, SDC on RTL and Early Timing Analysis features. DNI provides the Intel Quartus Prime Pro Software with a unified database that has a well-understood and easy-to-use data model, an application interface with clean separation from the database layer, and finally a uniform and comprehensive scripting interface to this database. The first application built on top of the Design Netlist infrastructure is the RTL Analyzer.

RTL Analyzer

  • WYSIWYG netlist viewer
  • Faster design loading
  • Optimization Hints
    • Visualize logic optimized out
    • Capable of handling over 10 million records
    • Fast filtering to focus on swept hierarchies
  • Unified cross probing across different design views
  • Connectivity Tracer enable user to explore logical connections in design
  • Object Constraints Viewer allows the user to cross-probe from a constraint to source file
  • Object Set Console which displays all currently selected, highlighted or colored nodes in the schematic viewer
  • Sweep Hints Viewer can be used to understand why some logic is “swept away”, including the root causes for various optimizations

SDC on RTL and Early Timing Analysis

  • Targets the Design Netlist for timing constraints
  • Write-once, use everywhere methodology
  • Allows constraints of hierarchical pins
  • Can constrain pins without knowledge of origin of signals
  • Works seamlessly with current synthesis and fitter SDC constraints
  • Post-synthesis static timing provides and early view of the core timing and verification of constraints
  • Enabled through DNI Infrastructure

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Board Awareness

Intel® Quartus® Prime Pro introduces the Board Awareness in the Platform Designer tool. With this flow the designer can select a user-defined board from within Quartus which will include details such as device family and device parts, IP presets, and pin configurations. These board files can also be selected in the Platform Designer. Using Board Awareness ensures that configurations for designs can be reused instead of starting from scratch every time and will not only accelerate design process, but also mitigate errors in board, IP, and pin configurations.

Introduction to Board Awareness Video

Board File Authoring Flow

There is also a board author flow for creating board files that is available with the Intel Quartus Prime Pro software. The Board Aware feature provides the solution for configuring all board functions and presets, including details such as device family and device parts, in one place. In this board author flow, users can create new board files and IP preset files used with the target board. These presets include pin assignments, I/O standards, IP settings, etc. and these presets will be automatically exported with the specified interfaces.

The board author flow allows you to export the presets for an existing board to be used in Platform Designer.

Board Awareness: Board Author Flow Video

Design Example Discovery

Design Examples are critical to early FPGA development. With the Intel® Quartus® Prime Pro Software, finding example designs is made easier through Design Example Discovery. This new flow allows you to find design examples from various repositories, including Online Design Examples from the Intel Design Store, Pre-installed Design Examples that are shipped as part of Quartus, as well as User Downloaded design examples that have been previously saved. The Design Example Discovery is part of the Quartus startup screen in the Open Example Project. From here a user can browse and filter the list of design examples, as well as preview the details of a selected design example.

When a design example is selected it will be automatically downloaded and extracted so it is ready to use as the starting point for the new design.

Introduction to Design Example Discovery Video

What’s New in Intellectual Property (IP)

Compute Interconnect (PCI Express and Compute Express Link)

  • Intel Agilex® 7 R-Tile:
    • Debug Tool Kit with Lane Margin support for PCI Express and CXL, Avalon® Streaming 5.0 x16 Performance Design
    • CXL 1.1 support for new features: base Hard IP (CST), Cache Line State Tracker

Network Interconnect (Ethernet)

  • Intel Agilex® 7 E-tile: 10M-10G MAC and PHY Soft IP

External Memory Interface

  • Intel Agilex® 7 M-series: DDR5 UDIMM / SoDIMM Support, ECC support for LPDDR5& HBM2e, HPS memory support

Communications Interconnect

  • Intel Agilex® 7: JESD204C data rate up to 32.44Gbps in F-tile

MACsec (Intel Agilex® 7 only)

  • New System Level example design released (25G/100G full duplex)
  • IP Statistic snapshot feature added

Video

  • HDMI: Pixel duplication/deduplication feature support. V2.1 support for Intel Agilex® 7 M-series
  • DisplayPort: DP1.4 HDCP support for Agilex 7. DP2.0 UHBR10 + HDCP support for Intel Agilex® 7
  • SDI: 12G-SDI support for Intel Agilex® 7 M-series

More Features

Compiler Features

  • Increased the maximum number of processors cores that the Compiler can use to 24 cores.
  • Added support for force statements in HDL code.
  • Added support for cross-module referencing (XMR) in HDL code.

Productivity Enhancements

  • Parameterizable Macros for External Memory Interface and FIFO IP.
  • IBIS Writer for Intel® Agilex™ 7 F-Series and I-Series devices.
  • Enhanced the Fixed Point DSP Register Packing Summary and Fixed Point DSP Register Packing Details reports to include additional information, such as names of the registers, the register, and reasons preventing register packing.
  • New Exploration Dashboard (Beta) command line tool to help you aggregate and compare compilation results from multiple projects to determine the best implementation.

Advanced Link Analyzer Features and Enhancements

  • Updated device support including support for Intel Agilex 7 F-Tile devices.
  • Enhanced the simulation engine with the following features:
    • Symbol burst error analysis.
    • FEC code word error analysis.
  • Enhanced the data viewers as follows:
    • Enabled viewing structured simulation data in tool tips.
    • Improved CSV eye diagram data import compatibility.

Power and Thermal Calculator Features and Enhancements

  • Added ability to import hierarchies from Intel Quartus Prime Power Analyzer (QPA).
  • Merged Navigation and Power Summary panels.
  • Enhanced the RAM page with additional information.

Partners

Questa*-Intel® FPGA Edition Software

The Questa*-Intel® FPGA Edition software from Mentor Graphics (A Siemens EDA company) is here! Questa*-Intel® FPGA Edition is the core simulation and debug engine of the Questa Verification Solution providing the latest in FPGA simulation technology. Questa-Intel FPGA Edition has up to 2.5x speedup for Verilog and 1.25x speedup for VHDL over the ModelSim*-Intel® FPGA Edition software. It is a full 64-bit version with support for both Windows 10 and Linux.

Documentation and Support

Find technical documentation, videos, and training courses for Intel® Quartus® Prime Design Software and other FPGA Development Tools.

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Additional Resources

Learn more about how to purchase Intel® FPGA development tools and software.

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Get the complete suite of Intel® FPGA design tools.

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This page lists all the online and instructor-led courses currently available.

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Find pricing information and purchase online.

Frequently Asked Questions About Intel® Quartus® Prime Design Software

Intel® Quartus® Prime Software enables a fast path to turning Intel® FPGA, SoC, and CPLD designs into reality. It provides tools and features needed to help with every step from design entry and synthesis to optimization, verification, and simulation. Check out the Intel Quartus Prime Software brochure for more details.

Intel® Quartus® Prime Pro Edition Software and Intel® Quartus® Prime Standard Edition Software require a paid license, but Intel® Quartus® Prime Lite Edition Software is license-free. A fixed-node subscription supports access to the Pro Edition and Standard Edition, was well as the Questa*-Intel® FPGA Edition with one year of maintenance. To obtain a license, go to the Intel® FPGA Licensing Support Center.

If you are ready to purchase a license or need advanced FPGA and SoC features—such as support for Intel Agilex® 7, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 LP device families—first purchase a paid license from the Intel® FPGA Licensing Support Center. To get started with the free version of Intel® Quartus® Prime Lite Edition Software or to download a licensed version, go to Intel Quartus Prime Software downloads.

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Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex​.

Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available ​updates. See backup for configuration details. No product or component can be absolutely secure.

Your costs and results may vary.