1G/10Gb Ethernet PHY Intel® FPGA IP

The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA). The Standard PCS implements the 1GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard. The 10G PCS implements the 10G Ethernet protocol as defined in the IEEE 802.3 2005 standard.

Read the V-Series Transceiver PHY IP Core user guide ›

Read the Intel® Arria® 10 Transceiver PHY user guide ›

1G/10Gb Ethernet PHY Intel® FPGA IP

The user can switch dynamically between the 1G and 10G PCS using the Intel® FPGA Transceiver Reconfiguration Controller IP core to reprogram the core. This IP core targets 1G/10GbE applications including network interfaces to 1G/10GbE dual speed SFP+ pluggable modules, 1G/10GbE 10GBASE-T copper external PHY devices to drive CAT 6/7 shielded twisted-pair cables and chip-to-chip interfaces.

Features

  • Integrated SGMII / 1000BASE-X / 10GBASE-R (10M-10Gb) Ethernet PCS and PMA.
  • Direct internal interface with Intel® FPGA 1G/10GbE (10M-10GbE) MAC for a complete single-chip solution.
  • User selectable 1G/10Gb data rates during runtime or automatic speed detection (parallel-detect) between 1Gb and 10Gb and reconfiguration by PHY IP, or data rate selection among 10/100/1000Mb with Ethernet auto-negotiation function.
  • 10Gb, 1G/10GbE, and 10M-10GbE (SGMII/1G/10GbE) options.
  • IEEE 1588 v2 option.
  • Synchronous Ethernet (Sync-E) option.
  • Serial transceiver clock and data recovery (CDR) recovered clock output signal exposed to the FPGA fabric for routing to a Sync-E jitter cleaner phase-locked loop (PLL).
  • Separate transmitter (TX) and receiver (RX) serial transceiver PLL reference clock inputs to allow optional external Sync-E jitter cleaner PLL to feed the cleaned clock to TX PLL reference clock input.
  • Receiver-link fault status detection.
  • Local serial loop-back from transmitter to receiver at serial transceiver for self-test.
  • High-performance internal system interfaces.
  • GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE (10M-10GbE) MAC, 8 bits at 125 MHz, and 72 bits at 156.25 MHz respectively for data transfer.
  • Intel® FPGA Avalon® Memory-Mapped (Avalon-MM) 32 bit interface for slave management.

IP Status

 

Status

Production

Ordering Codes

1G/10Gb Ethernet PHY Intel® FPGA IP

IP-10GBASEKRPHY

V-Series Transceiver PHY IP Core

IP-10GMRPHY
View all Show less

Related Links

Documentation

  • Complete 1G/10GbE and 10M-10GbE PHY solution available to start your design quickly.
  • Register transfer level (RTL) and post-fit functional simulation for Intel® FPGA-supported Verilog HDL and VHDL simulators.
  • 1G/10GbE and 10M-10GbE MAC and 1G/10GbE and 10M-10GbE PHY verification testbench and design example.
  • Configuration and generation via GUI-based parameter editor.
  • Typical expected performance and resource utilization figures for this IP core are provided in the V-Series Transceiver PHY IP Core user guide.
  • Intel® FPGA IP Release Notes ›

Development Boards

Intel® Arria® 10 GX FPGA Development Kit ›

Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit ›

Transceiver Signal Integrity Development Kit, Stratix® V GX Edition ›

Device Support

Additional Resources

Find IP

Find the right Intel® FPGA Intellectual Property core for your needs.

Technical Support

For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

IP Evaluation and Purchase

Evaluation mode and purchasing information for Intel® FPGA Intellectual Property cores.

Designing with Intel® FPGA IP

Learn more about designing with Intel® FPGA IP, a large selection of off-the-shelf cores optimized for Intel® FPGAs.

IP Base Suite

Free Intel FPGA IP Core licenses with an active license for Intel® Quartus® Prime Standard or Pro Edition Software.

I-Tested

Intel awards the interoperability-tested or I-Tested certification to verified Intel FPGA IP or Intel FPGA Design Solutions Network member IP cores.

Intel® FPGA Partner IP

Browse catalog of Intel® FPGA partner intellectual property cores in the Intel® Solutions Marketplace.

Design Examples

Download design examples and reference designs for Intel® FPGA devices.

IP Certifications

Intel is committed to providing Intellectual Property cores that work seamlessly with Intel® FPGA tools or interface specifications.

Contact Sales

Get in touch with sales for your Intel® FPGA product design and acceleration needs.

Show more Show less
Compare Products