Interlaken Intel® FPGA IP
The Interlaken Intel® FPGA IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high bandwidth throughput in their systems. This pre-built, ready-to-go IP building block shortens the design cycle resulting in faster time to market.
Read the Interlaken (2nd generation) Intel® FPGA IP user guide ›
Read the 50G Interlaken MegaCore Function user guide ›
Read the 50G Interlaken Design Example user guide ›
Read the 100G Interlaken MegaCore Function user guide ›
Read the 100G Interlaken Design Example user guide ›
Read the Interlaken IP Core (2nd generation) Design Example user guide ›
Read the F-Tile Interlaken Intel® FPGA IP user guide ›
Read the F-Tile Interlaken Intel® FPGA IP Design Example user guide ›
Interlaken Intel® FPGA IP
Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond.
Interlaken Intel® FPGA IP core is ideal for:
- Multi-terabit routers and switches for access
- Carrier Ethernet and data center applications that demand IP configurability to optimize for various traffic profiles
- Scalability for next-generation platforms
Intel has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate new protocol features to provide customers with robust and easy-to-implement Interlaken IP solutions. Intel now offers up to 600G Interlaken IP.
With the release of Intel's next-generation Intel® Arria® 10 FPGAs and SoC FPGAs, the Intel® FPGA Interlaken IP Portfolio accomplishes major development milestones: third-generation soft IP (includes media access control (MAC)) and second-generation hardened IP (includes physical coding sublayer (PCS) / physical medium attachment (PMA)). These seasoned, battle-tested cores continue to provide the additional robustness and maturity required for new, more intelligent systems.
- Data rate selection up to 25.78125 Gbps (NRZ) OR 56 Gbps (PAM4)
- Multi-lane configuration up to 24 lanes
- Interleave packet mode support
- Enhanced scheduling
- Multi-segment or Start-of-Packet (SOP) alignment user interface options
- I/O controllable burst settings (Min, Max, Short)
- Programmable meta frame lengths
- Up to 256 logical channels
- Multiple-use field access
- In-band and out-of-band flow control (calendar page options)
- Advanced error handling and error injection capabilities
- Fully integrated IP (MAC, PCS, and PMA layers)
- Tunable pre-emphasis and equalization settings
- Custom IP deliveries available to optimize for various application needs
- Supports ILA mode