DDR4 EMIF Intel® FPGA IP

DDR4 offers higher performance, density and lower power and more control features compared to DDR3. Intel FPGA DDR4 EMIF IP offers solutions for high computing memory needs for client and data center systems.

DDR4 EMIF Intel® FPGA IP

Intel® Agilex™ FPGAs & SOCs, Intel® Stratix® 10 FPGAs & SOC and Intel® Arria® 10 FPGAs implement DRAM hardened memory controller & PHY. Hardening the controller & PHY offers several advantages which include:

  • Shorter development cycles and faster time to market due to pre-closed timing
  • More FPGA fabric logic resources available for user application
  • Improved fmax, efficiency and latency
  • Low power solution

Features

Component

Intel Agilex SOC FPGA

Intel Stratix 10 SOC FPGA

Controller & PHY
  • Hard
  • Hard

Memory format & Max data width
  • Up to 72-bits in multi-rank Discrete and DIMM format
  • Up to 72-bits in multi-rank Discrete and DIMM format
  • Supports Ping Pong PHY

User logic clock speed
  • Quarter-Rate
  • Quarter rate
  • Half rate

ECC
  • 8-bit soft ECC code with single error correction, double error detection (SECDED)
  • ECC is based on Hamming coding scheme
  • 8-bit soft ECC code with single error correction, double error detection (SECDED)
  • ECC is based on Hamming coding scheme

Controller Features
  • Open Page policy
  • Additive latency
  • Data reordering
  • Pre-emptive bank management
  • Bank interleaving
  • Starvation counter
  • Open Page policy
  • Additive latency
  • Data reordering
  • Pre-emptive bank management
  • Bank interleaving
  • Starvation counter

Example design to simulate & Validate IP

✓

✓

PHY-only support

✓

✓
IP-XACT support ✓

✓
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Debug Features

EMIF Debug toolkit features include the below basic and advanced debug capabilities:

  • Viewing calibration margin, status, pin delay & VREF settings
  • Re-running calibration, traffic generator, driver margining
  • Updating delay settings, termination settings
  • Configurable Traffic Generator to send test traffic patterns

Specifications

Memory Device

Intel Agilex

Intel Stratix 10

Intel Arria 10

DDR4

3200 MT/s

2666 MT/s

2400 MT/s
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IP Quality Metrics

Basics

Year IP was first released

2004

Latest version of Intel® Quartus® Prime software supported

21.3

Status

Production

Deliverables

Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Simulation files

    Timing and/or layout constraints

    Documentation with revision control

Y for all

Any additional customer deliverables provided with IP

Testbench and design examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog/System Verilog

Testbench language

Verilog/VHDL

Software drivers provided

N

Driver OS Support

N/A

Implementation

User interface

Avalon® memory-mapped interface

IP-XACT metadata

Y

Verification

Simulators supported

Questasim, NCSim, VCS, Xcelium

Hardware validated

Intel Agilex, Stratix 10, Arria 10

Industry standard compliance testing performed

N/A

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

N/A

If yes, on which Intel FPGA device(s)

N/A

Interoperability reports available

N/A
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