MAX® V CPLDs

MAX® V CPLDs offer a unique, non-volatile architecture, delivering low power and on-chip features, suitable for Intel Edge-Centric applications.

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MAX® V CPLDs

New Features offered by MAX® V CPLDs (vs. previous generation MAX® CPLDs)

These new features allow you to integrate multiple control path applications onto a single device. With its mix of low price, low power, and high performance features, MAX® V CPLDs deliver the market’s best value.

Architecture

Logic element (LE) converted to RAM, on-chip oscillator, 1.2-V LVCMOS, and LVDS output support.

Cost

Prices starting under $1. Lower total system cost due to the architecture that integrates more external functions that were previously implemented in discrete logic ASSPs. Lower total bill of materials (BOM) costs as the device requires as few as one power supply (Vcc-core).

Extended Battery Life

Extended battery life with static power as low as 45 µW.

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Top Five CPLD Control Path Applications

Read CPLD white paper

I/O Expansion

Perform I/O decoding, efficiently increasing the available I/O capability of another standard device at a low cost.

Interface Bridging

Translate bus protocols and voltages between incompatible devices at the lowest possible cost.

Power Management Control

Manage the power-up sequencing and monitoring of other devices on the board.

Configuration and Initialization Control

Control the configuration or initialization of other devices on the board.

Analog Control

Digital control of analog standard devices (light, sound, or motion) via pulse-width modulator (PWM) without needing a digital-to-analog converter (DAC).

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Additional Resources

Explore more content related to Intel® FPGA devices such as development boards, intellectual property, support and more.

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