Intel® Stratix® 10 FPGA Features
Intel® Stratix® 10 FPGAs and SoCs deliver the highest performance along with the highest levels of system integration. Learn more about the unique capabilities and breakthrough advantages that Intel® Stratix® 10 devices deliver to enable next-generation, high-performance systems in a wide-range of applications below.
Intel® Hyperflex™ FPGA Architecture
To address the challenges presented by next-generation systems, Intel® Stratix® 10 FPGAs and SoCs feature the new Intel® Hyperflex™ FPGA Architecture, which delivers 2X the clock frequency performance and up to 70% lower power compared to previous-generation, high-end FPGAs.1
The Intel® Hyperflex™ FPGA Architecture introduces additional by passable registers everywhere throughout the FPGA fabric. These additional registers, called Hyper-Registers, are available on every interconnect routing segment and at the inputs of all functional blocks. Hyper-Registers enable three key design techniques to achieve the 2X core performance increase:
- Fine grained Hyper-Retiming to eliminate critical paths.
- Zero latency Hyper-Pipelining to eliminate routing delays.
- Flexible Hyper-Optimization to achieve the best performance.
When you use these techniques in your design, the Hyper-Aware design tools automatically use the Hyper-Registers to achieve maximum core clock frequency.
Intel EMIB Packaging Technology for Intel® Stratix® 10 Devices
Intel’s patented Embedded Multi-Die Interconnect Bridge (EMIB) technology enables effective in-package integration of system-critical components, such as analog, memory, ASICs, CPU, and so on. EMIB technology offers a simpler manufacturing flow, compared to other in-package integration technologies. Additionally, EMIB eliminates the need to use through silicon vias (TSV) and specialized interposer silicon enabling a solution that offers higher performance, less complexity, and superior signal and power integrity. EMIB uses a small silicon chip embedded in the substrate to provide ultra-high density interconnect between die. Standard Flip Chip assembly connects power and user signals from the chip to package balls. This approach minimizes interference from core switching noise and crosstalk to deliver superior signal and power integrity.
For details on the specific implementation of this technology on the upcoming Intel® Stratix® 10 device family, see the Transceivers section.
Transceiver Tile Variants
|Intel® Stratix® 10 Device Variants||GX, SX||GX, SX, TX, MX||TX, MX||DX|
|Maximum Transceivers per Tile*||24||24||24||20|
|Maximum Chip-to-Chip Data Rates(NRZ/PAM4)||17.4 Gbps/-||28.3 Gbps/-||28.9 Gbps/57.8 Gbps||16 GT/s/-|
|Maximum Backplane Data Rates(NRZ/PAM4)||12.5 Gbps/-||28.3 Gbps/-||28.9 Gbps/57.8 Gbps||16 GT/s/-|
|Insertion Loss at Maximum Data Rate||Up to 18 dB||Up to 30 dB||Up to 35 dB||Refer to PCIe* Gen4 and UPI specs and conditions
PCIe* Gen1, 2, and 3 with x1, x4, x8, and x16 lane support
10G Fire Code FEC Hard IP
PCIe* Gen1, 2, and 3 with x1, x4, x8, and x16 lanes
4 Physical functions and
2K Virtual functions
10G Fire Code FEC Hard IP
|10/25/100 GbE MAC with RS-FEC and KP-FEC||Intel® Ultra Path Interconnect (Intel® UPI)
PCIe* Gen1, 2, 3, and 4 with x1, x4, x8, and x16 lanes
8 Physical functions
2048 Virtual functions
Port bifurcation support for 2x8 Endpoint or 4x4 rootport
Transaction Layer (TL) bypass features
Configuration via Protocol (CvP) Initialization
Shared virtual memory
|*Please refer to Intel® Stratix® 10 device Product Tables for exact number of transceivers available in a device & package combination.|
Interconnect to CPUs, ASICs, and ASSPs
Targeting high-performance acceleration applications, increasingly used in Data Center, Networking, Cloud Computing, and Test & Measurement markets, Intel® Stratix® 10 DX FPGAs feature hard, and soft intellectual property blocks supporting both UPI and PCIe* Gen4 interfaces.
A low latency, high performance coherent interface is achieved when connecting the FPGA to selected Intel® Xeon® Scalable processors via Intel® Ultra Path Interconnect (Intel® UPI), while the non-coherent interface takes advantage of any PCI Express* (PCIe*) Gen4 capable device.
Detailed features of Intel® Stratix® 10 FPGAs and SoCs interconnect solution:
- Hard Intel UPI intellectual property blocks in Intel® Stratix® 10 devices, supporting Cache Agent, and Home Agent soft IP.
- Hard PCI Express Gen4 x16 intellectual property blocks, with features such as Endpoint and Root Port bifurcation modes, virtualization support for Single-Root I/O virtualization (SR-IOV), Virtual I/O device (VIRTIO), Intel® Scalable I/O Virtualization (Intel® Scalable IOV), and Transaction Layer bypass mode.
With Intel® Stratix® 10 devices, digital signal processing (DSP) designs can achieve up to 10 tera floating-point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations. This unprecedented degree of computational throughput is made possible by a hardened floating-point operator within each DSP block. It is initially introduced in the Intel® Arria® 10 device family and now extended to deliver an order of magnitude greater throughput in Intel® Stratix® 10 FPGAs and SoCs. Read the Intel® Stratix® 10 FPGA and SoC DSP backgrounder.
Intel® Stratix® 10 Device DSP Block
AI Tensor Block
Using Intel® Stratix® 10 NX FPGA, AI acceleration designs can achieve up to 143 INT8/Block Floating Point 16 (Block FP16) TOPS/TFLOPS at ~1 TOPS/W or 286 INT4/Block Floating Point 12 (Block FP12) TOPS/TFLOPS at ~2 TOPS/W2. This computational throughput is made possible by a new type of AI-optimized computation block called the AI Tensor Block. The AI Tensor Block’s architecture contains three dot-product units, each of which has ten multipliers and ten accumulators, for a total of 30 multipliers and 30 accumulators within each block. The AI Tensor Block’s architecture is tuned for common matrix-matrix or vector-matrix multiplications used in a wide range of AI computations, with capabilities designed to work efficiently for both small and large matrix sizes.
Intel® Stratix® 10 FPGAs and SoCs ensure high reliability and provides SEU mitigation capabilities.
- Advanced SEU Detection (ASD).
- Sensitivity processing.
- Hierarchy tagging.
- Fault injection.
- Use to characterize and improve your designs.
Intel® Stratix® 10 SoC Development Tools
The Intel® SoC FPGA Embedded Development Suite (SoC EDS) featuring ARM* Development Studio* 5 (DS- 5*) supports Intel® Stratix® 10 SoCs, providing heterogeneous debug, profiling, and whole-chip visualization. The SoC EDS unifies all software debugging information from the CPU and FPGA domains and presents them in an organized fashion within the standard DS-5 user interface. The toolkit gives users an unprecedented level of debugging visibility and control that delivers substantial productivity gains.
To learn more, visit the Intel® Stratix® 10 SoC page.
Get information about hardware solutions and tools offered by Intel to accelerate the design process.
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Product and Performance Information
Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.
Based on internal Intel estimates.
Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.in/benchmarks.
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