|Feature||Stratix® V E FPGA||Stratix® V GS FPGA||Stratix® V GX FPGA|
|High-performance adaptive logic modules (ALMs)||359,200||262,400||359,200|
|Variable-precision DSP blocks (18x18)||704||3,926||798|
|M20K memory blocks||2,640||2,567||2,660|
|External memory interface||x||x||x|
|Fractional phase-locked loop (PLL)||x||x||x|
|Single event upset (SEU) mitigation||x||x||x|
|PCI Express* Gen3, Gen2, Gen1 hardened IP blocks hardened IP block(s)||Up to 2||Up to 4|
|Embedded hard IP blocks||x||x|
|Transceivers (Data rate / number of transceiver channels)||14.1 Gbps / 48||14.1 Gbps / 66|
The Stratix® V FPGA family includes the following device variants:
- Stratix® V GX FPGAs with transceivers: Integrate up to 66 full-duplex, 14.1 Gbps transceivers and up to 6 x72 bit DIMM DDR3 memory interfaces supporting 933 MHz.
- Stratix® V GS FPGAs with enhanced digital signal processing (DSP) capabilities and transceivers: Integrate up to 3,926 18x18, high-performance, variable-precision multipliers, 48 full-duplex, 14.1 Gbps transceivers, and up to 6 x72 bit DIMM DDR3 memory interfaces supporting 933 MHz.
- Stratix® V E FPGAs: Up to 950K logic elements (LEs), 52-megabit (Mb) RAM, 704 18x18 high-performance, variable-precision multipliers, and 840 I/Os.
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