Describes the internal cable interface for USB 3.0 connections in a desktop—focusing on the electrical and mechanical requirements of the connector—and cable assembly. The detailed daughter card or direct-cable implementation is out of the scope of this documentation.
This is a final version of the physical layer (PHY) interface for PCI Express* (PIPE) and USB 3.0 architectures specification that supports PCI Express* and USB 3.0 architectures. The PIPE specification describes a standardized interface between PHY and media access control (MAC) implementations for PCIe* Gen2 and USB 3.0. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.
This specification describes the register-level host controller interface for all USB speeds and includes a description of the hardware/software interface between the system software and the host controller hardware.
The specification is intended for hardware component designers, system builders, and device driver (software) developers. The reader is expected to be familiar with the current USB specification revisions.
This specification describes the registers and data structures used to interface with the USB Type-C connectors on a system. The system software component is referred to as the OS Policy Manager (OPM) in this specification.
This specification is intended for hardware component designers, system builders, and device driver (software) developers. The reader is expected to be familiar with USB Type-C and USB Power Delivery (PD) specifications. In spite of due diligence, there may exist conflicts between this specification and either one or both of the above mentioned specifications. In such cases the USB Type-C and USB Power Delivery (PD) take precedence.
The EHCI compliance testing program measures an EHCI controller implementation for conformance to the EHCI specification and evaluates the functionality of the EHCI controller function of a USB 2.0 host controller. It does not evaluate the functionality of the USB companion controllers.
USB 2.0 Transceiver Macrocell Interface (UTMI) › The UTMI specification covers the physical interface and many operational aspects of the USB 2.0 Transceiver Macrocell (UTM). The intent of the UTMI is to accelerate USB 2.0 High-speed, Full-speed, and Low-speed peripheral development. This document defines an interface to which ASIC and peripheral vendors can develop. ASIC vendors and foundries will implement the UTM and add it to their device libraries. Peripheral and IP vendors will be able to develop their designs, insulated from the high-speed, and analog circuitry issues associated with the USB 2.0 interface, thus minimizing the time and risk of their development cycles.