Intel® Agilex™ FPGA 116G PAM4 Transceiver I/O Demonstration

Intel® Agilex™ FPGA and SoC devices offer new levels of performance using Intel’s Advanced 10nm SuperFin Technology including transceiver rates up to 116Gbps to support demanding bandwidth requirements in next-generation data center, enterprise, and networking environments.

Transcript

Hi, I'm Kevin Zhang, a Marketing Manager at Intel. Today we want to show you the Intel Agilex FPGA's high-speed transceiver I/O results. In particular, this demo demonstrates compliance with the CEI-112G-LR-PAM4 specification.

This demo shows the performance of our latest high-speed transceiver built using Intel's advanced 10nm SuperFin technology. I have Sree in the lab today to perform the demo for you.

Hi, my name is Sree Balaji Girisankar, an application engineer at Intel. This is the transmitter setup diagram with Intel Agilex I-Series FPGA ES0 device.

Lane 1 and 2 are running in an internal serial loopback mode, and Lane 3 is connected to an ISI channel with 38dB bump-to-pump insertion loss. Lane 0 is connected to the high-speed oscilloscope.

And here, you can see a 116G PAM4 eye, compliant to the highest rate of the CEI-112G specification. This higher data rate provides added margin and enables support for emerging standards.

As you can see, the 116G transmitter is complaint across all 106.25, 112, and 116 gigabit per second data rates.

These 116G PAM4 Long Reach capable transceivers are incorporated into Intel Agilex I-Series FPGAs, with as many as eight CEI-116G capable transceivers per device and hardened 100/200/400G Ethernet interfaces. These FPGAs are optimized for bandwidth-intensive applications.

The transmitter is only a part of the story. Reliable receivers are even harder to achieve with these high-speed data rates.

This is the receiver setup diagram with Intel Agilex I-Series FPGA ES0 device. Lane 1, 2, and 3 are running in an internal loopback mode. For Lane 0, we've set up a full, bidirectional channel demonstration.

We transmit a 116Gbps PRBS31 data pattern from our DAC-based transmitter to a channel and back to the transceiver's advanced ADC-based receiver. We have more than 38dB of insertion loss in total from bump to bump on the FPGA package. Even with this insertion loss, we can see an excellent received PAM4 signal quality with a bit error rate that's three orders of magnitude better than the specification.

Amazing result, isn't it? For more information about this 116G PAM4 Long Reach transceiver demonstration, or to learn more about Intel Agilex FPGAs, please contact your local Intel Salesperson.