Stratix® Series FPGA Low Power Consumption Features
As process technologies become smaller and smaller, power and thermal management become more and more important, especially in a high-performance, high-density FPGAs. To reduce power consumption in new generations of the Stratix® series FPGAs, Intel® FPGA developed several new technologies. The main power consumption reducing technologies (found in Stratix® III FPGA and later families) are:
Programmable Power Technology
Recent Stratix series FPGAs feature Programmable Power Technology, to minimize power and deliver highest performance where needed. Figure 1 shows how Programmable Power Technology works at the block level—logic, memory, or digital signal processing (DSP).
Figure 1. Standard FPGA Fabric vs. Stratix Series FPGA Fabric with Programmable Power Technology
- In standard FPGAs, all the logic blocks are designed to run at only one speed—the highest possible speed (as depicted by the yellow blocks)—resulting in excessively high power consumption.
- In an FPGA design, very few paths (on average only 20 percent) are timing critical. Using Programmable Power Technology, all logic blocks in the array, except those designated as timing critical, are set to low-power mode (as depicted by the blue blocks). With only the few logic blocks that are timing critical set to high-speed mode, Programmable Power Technology enables Stratix series FPGAs to deliver the lowest power and the highest performance.
For any design, Quartus® II software determines the slack available in each path of the circuit to automatically set the transistors (within blocks) to the appropriate mode—high performance or low power—by adjusting the back bias voltage of the transistor. This makes the transistor harder to turn on, thereby minimizing subthreshold leakage currents and unwanted static power. Figure 2, at a very high level, shows how Quartus II software controls the transistors to switch between high-performance and low-power mode.
Figure 2. Quartus II Software Minimizes Power and Maximizes Performance
For example, here is how Intel Quartus II software sets an NMOS transistor in the core of a Stratix series FPGA:
- Low-power mode—Quartus II software reduces the back bias voltage (making it more negative), which makes the transistor harder to turn on. This results in less leaky transistors and saves power in most of the design paths
- High-performance mode—Quartus II software increases the back bias voltage (making it less negative), which makes the transistor easier to turn on in the few timing-critical paths to help meet the design's specified timing constraints and deliver the maximum performance
DDR3 and Dynamic On-Chip Termination (OCT)
Enabled by read/write leveling, the newest generations of Stratix series FPGAs easily interface to DDR3 memories operating at 1.5 V, thereby reducing static power by 30 percent over DDR2 memories at 1.8 V.
Additionally, dynamic OCT further reduces static power by on a typical 72-bit DIMM (72 DQ and 18 DQS pins) by turning on and off series termination (RS) and parallel termination (RT ) dynamically during data transfer (see Figure 3). As an example, by combining the effects of DDR3 voltage shrink and DOCT, a Stratix IV FPGA, on a typical 72-bit DIMM, lowers parallel OCT static power by 65 percent at 1,067 Mbps when compared to a standard FPGA.
Figure 3. Dynamic OCT for Memory Interface
- During the write cycle, RS is turned on and RT is turned off to match the line impedance
- During the read cycle, RS is turned off and RT is turned on as the Stratix series FPGA implements the far-end termination of the bus
For additional information on DDR3 and dynamic OCT, refer to the 40-nm Power Management and Advantages white paper (PDF).
Process and Circuit Technologies
Stratix III and later Stratix series FPGAs utilize the latest process and circuit techniques along with major circuit and architecture innovations to minimize power and still deliver the highest performance of any FPGA. Some of the technologies employed include multi-threshold transistors, variable gate-length transistors, low-k dielectric, triple-gate oxide (TGO), super-thin gate oxide, and strained silicon. For additional information on these process and circuit technologies, refer to the 40-nm Power Management and Advantages white paper (PDF).
PowerPlay Power Analysis and Optimization Tool
The Quartus II software PowerPlay power analysis and optimization tool helps keep the total power consumption of your designs to a minimum. Intel FPGA began offering advanced power optimization capabilities in Quartus II software in 2005, and it immediately provided an average 25 percent reduction in dynamic power in our customers’ designs.
Since then, the PowerPlay power analysis and optimization tool has been improved with the addition of intelligent decision making in synthesis, placement, and routing. Today, by working in conjunction with Programmable Power Technology in the Stratix series silicon, the power consumption minimizing capability of PowerPlay power optimization is the best it has ever been. To learn more, visit the Power Optimization for Stratix III FPGAs web page.
- 40-nm power management and advantages white paper (PDF) ›
- Power optimization for Stratix III FPGAs ›
- Stratix III Programmable Power white paper (PDF) ›
- Overview of Quartus II PowerPlay power analysis & optimization technology ›
- Stratix III power management design guide (PDF) ›
- Power optimization in Stratix III FPGAs (PDF) ›
- PowerPlay early power estimators ›
- Quartus II power estimation (demo) ›
- Stratix IV FPGAs ›
- Stratix III FPGAs ›