Intel's 28 nm Stratix® V FPGAs deliver high bandwidth, high level of system integration, and ultimate flexibility with reduced cost and low total power for high-end applications.
Feature | Stratix® V E FPGA | Stratix® V GS FPGA | Stratix® V GX FPGA |
---|---|---|---|
High-performance adaptive logic modules (ALMs) | 359,200 | 262,400 | 359,200 |
Variable-precision DSP blocks (18x18) | 704 | 3,926 | 798 |
M20K memory blocks | 2,640 | 2,567 | 2,660 |
External memory interface | x | x | x |
Partial reconfiguration | x | x | x |
Fractional phase-locked loop (PLL) | x | x | x |
Design security | x | x | x |
Single event upset (SEU) mitigation | x | x | x |
PCI Express* Gen3, Gen2, Gen1 hardened IP blocks hardened IP block(s) | Up to 2 | Up to 4 | |
Embedded hard IP blocks | x | x | |
Transceivers (Data rate / number of transceiver channels) | 14.1 Gbps / 48 | 14.1 Gbps / 66 |
The Stratix® V FPGA family includes the following device variants: