Report Fmax Summary Command

The Timing Analyzer computes f_MAX for all paths where the same clock drives the source and destination registers or ports. The Timing Analyzer ignores paths of different clocks and generated clocks. For paths between a clock and its inversion, the Timing Analyzer computes f_MAX as if the rising and falling edges scale along with f_MAX, such that the duty cycle (in terms of a percentage) is maintained. You must constrain all clocks for accurate timing analysis.

The Restricted Fmax can indicate a "Limit due to hold check." Typically, hold checks do not limit the maximum frequency (f_MAX) because these checks are for same-edge relationships, and therefore independent of clock frequency. An example of this occurs when launch equals zero and latch equals zero. However, with an inverted clock transfer, or a multicycle transfer (such as setup=2, hold=0), then the hold relationship is not a same-edge transfer and changes with the clock frequency.