CLK-30031: Input Delay Assigned to Clock

Description

Violations of this rule identify clock ports that have an input delay constraint assigned. The Compiler ignores input delays set on clock ports because clock-as-data analysis takes precedence.

Recommendation

Remove the input delay constraint.

Severity

Medium

Tags

Tag Description
sdc Design rule checks related to SDC validity checking.
system Design rule checks which validate full-system design.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®