TMC-20205: Endpoints of Paths Failing Setup Analysis with Explicit Power-Up States that Restrict Retiming

Description

Violations of this rule indicate endpoints of paths that fail setup analysis with explicit power-up states that might restrict retiming. A path might not be fully optimized by the retimer if either of its endpoints has a power-up state. Refer to Initial Power-Up Conditions in the Intel Hyperflex Architecture High-Performance Design Handbook for more information.

Parameters

Name Description Type Default Value Min Value Max Value
maximum_setup_slack Reports a violation for timing paths that have a setup slack below the value of this parameter. double 0.0    
to_clock_filter Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. string *    
minimum_number_of_adders Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. integer 3    
minimum_number_of_soft_mult_chains Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. integer 2    

Recommendation

Consider applying the IGNORE_REGISTER_POWER_UP_INITIALIZATION ON setting to registers or their hierarchy to allow retiming optimizations to improve performance.

Severity

Medium

Tags

Tag Description
retime Design rule checks which pertain to the Compiler's Retime stage.

Device Family

  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®
  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX