Interface Protocols
Interface protocols enable chip-to-chip, board-to-board, or box-to-box connectivity in system designs. Protocol intellectual property (IP) solutions from Intel and our partners satisfy the needs of a broad spectrum of applications and leverage the integrated transceivers in our FPGA and ASIC devices. Interface protocol solutions are delivered as licensable IP cores and reference designs as well as no-cost megafunctions and design examples.
Visit our Transceiver Protocols section to learn more about the integrated transceivers and their supporting interface protocol solutions.
Designs targeted for the Intel® MAX® 10 FPGA device family and its development kits are available in the Design store.
| Design Examples | Device Targeted | Development Kits Supported | Qsys Compliant | Quartus Prime or Quartus® II Version |
|---|---|---|---|---|
Constraint RGMII Interface of Triple Speed Ethernet with the External PHY Delay Feature |
Cyclone® II, Cyclone® III, Cyclone III LS, Cyclone® IV GX, Stratix® II, Stratix II GX, Stratix® III, Stratix® IV, Arria® GX, Arria® II GX | Stratix IV GX FPGA Development Kit, Arria II GX FPGA Development Kit | - | 10.1 |
GPIO Pin Expansion Using I2C Bus Interface in MAX II CPLDs: AN 494 (PDF) |
MAX II | - | - | - |
| Cyclone II, Cyclone V | - | ✓ | 12.1 | |
I2C Battery Gauge Interface Using MAX II CPLDs: AN 493 (PDF) |
MAX II | - | - | - |
| MAX II | - | - | 10 | |
| MAX II | - | - | - | |
| Stratix IV GX | Stratix IV GX FPGA Development Kit | ✓ | 12.1 | |
| Cyclone III, Stratix IV GX | Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit, CV GT FPGA Development Kit | ✓ | 12 | |
| Cyclone III | Embedded Systems Development Kit, Cyclone III Edition | - | 9.1 | |
| Cyclone III | Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit | - | 13.1 | |
| Cyclone III | Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition | - | 10.1 | |
| - | - | - | All | |
| - | - | - | All | |
PCI Target Termination Examples for pci_mt32 and pci_t32 MegaCore Functions |
- | - | - | All |
POS-PHY Level 4 (SPI-4.2) External PLL Sharing Design Example |
Stratix IV GX | - | - | 9.1 |
RapidIO: Maintenance Host to System Maintenance Agent Bridge |
- | - | - | All |
Serial Peripheral Interface (SPI) Host in MAX II CPLDs: AN 485 (PDF) |
MAX II | - | - | 7.2 |
| MAX II | MDN-B2 | - | - | |
| MAX II | - | - | - | |
| MAX II | - | - | 10 | |
TSE: Implement Reset Sequence in TSE Using ALTGX as Transceiver |
Stratix IV GX | - | - | 9.1 SP1 |
TSE: Implement Reset Sequence in TSE Using ALTLVDS as Transceiver |
Stratix IV GX | - | - | 9.1 SP1 |
| Stratix IV GX, Arria II GX | - | - | 9.1 SP1 | |
| MAX II | MDN-B2 | - | 7.2 |