DSP Builder for Intel® FPGAs is a digital signal processing (DSP) design tool that enables Hardware Description Language (HDL) generation of DSP algorithms directly from the MathWorks Simulink* environment onto Intel® FPGAs. The tool generates high quality, synthesizable VHDL/Verilog code from MATLAB functions, and Simulink models. The generated Register Transfer Level (RTL) code can be used for Intel® FPGA programming. DSP Builder for Intel® FPGAs is widely used in radar designs, wireless and wireline communication designs, medical imaging, and motor control applications.
DFT (Discrete Fourier Transform) block with example to demonstrate use in 5G wireless.
Read Access (RA) controls for memory blocks shut off clock to memory to reduce power consumption. FFT IPs automatically use the RA feature where appropriate.
Reduced overhead for back-to-back DSP Builder FFTs.
DSP Builder Pro edition support for Intel® Cyclone® V (compile generated RTL with Quartus Prime Standard).
Install DSP Builder stand-alone to create and simulate DSP Builder models and generate RTL (Quartus-related features not available). Later connect Quartus to DSP Builder by setting environment variable.
Supported with the Intel® Quartus® Prime Design Software Pro/Standard Edition software.
Download Pro Edition to target the latest Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
Download Standard Edition to target Intel® Arria® 10, Stratix® V, Cyclone® V, Intel® Cyclone® 10 LP, and Intel® MAX® 10 devices.
Additional DSP Builder and MATLAB licenses are required. Purchase DSP Builder license here. Purchase MATLAB license here.