Intel® FPGA Development Tools
Fast-track Your Embedded Software Development
The Intel® SoC FPGA Embedded Development Suite (SoC EDS) is a comprehensive tool suite for embedded software development on Intel® SoC FPGAs. It comprises of development tools, utility programs, and design examples to jump-start firmware and application software development.
SoC EDS Enables You to:
- Leverage the power of Arm* Development Studio 5* (DS-5*) Intel® SoC FPGA edition to code, build, debug, and optimize your application
- Expedite SoC FPGA embedded systems development with utility programs and runtime software
- Jump-start development with Bare metal and Linux* application examples
What's New
The following updates are included as part of the release of Intel® SoC EDS v18.1.
FPGA-Adaptive Debug
The FPGA-adaptive debug is a powerful feature that gives a system-wide view of the SoC, allowing you to cross-trigger between the hard processor system (HPS) and the FPGA with ease.
Update to SD Card Image
The SD card image is now available as a separate download for the Golden System Reference Design (GSRD) and for SoC EDS. Download for free at Rocketboards.org.
Features
Arm* Development Studio 5 Intel® SoC FPGA Edition
Powerful Eclipse IDE based on Arm* DS-5 is power packed with features. Code, build, debug, and optimize in one IDE!
Hardware Libraries
Easy access to low-level hardware for configuration and control.
Configuration Tools
Intel® FPGA-specific SoC configuration tools to improve productivity.
Design Examples
Golden Hardware Reference Design (GHRD) for SoC FPGA development kits. U-Boot, Linux*, and Bare metal reference examples to jump start your development.
Getting Started
Intel® SoC FPGA Embedded Development Suite (SoC EDS) is available in two editions: Standard Edition and Pro Edition.
Intel® FPGA Design Tools and Software
Browse other FPGA design tools and resources available from Intel. OpenCL™ and the OpenCL™ logo are trademarks of Apple Inc. used by permission by Khronos.
Foundational Software and Simulation Tools
High Level Design