Article ID: 000073874 Content Type: Troubleshooting Last Reviewed: 07/21/2022

Why does DDR calibration fail on Intel® Arria® 10 SoCs when using early I/O release?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Software version 16.0 and earlier, RZQ pins for Intel® Arria® 10 SoC designs can be located on I/O banks not enabled for early I/O release. DDR calibration will fail if the related RZQ pin is located on an I/O bank not enabled for early I/O release.

    Resolution

    To work around this problem, ensure RZQ pins for HPS External Memory Interfaces are located on I/O banks enabled for early I/O release.

    This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Software

     

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 SX SoC FPGA