You may want different Intel Stratix 10 transceiver PMA settings than those specified in the Intel Stratix 10 L-Tile/H-Tile Native PHY IP.
You can add Intel Stratix 10 L-Tile and H-Tile device transceiver PMA Quartus® Settings File (QSF) assignments using the method below.
You can add the QSF assignments using the syntax example below.
Syntax:
set_instance_assignment -name HSSI_PARAMETER "${full_attribute_name}={chosen_attribute_value} " -to ${tx_pin}
Example:
set_instance_assignment -name HSSI_PARAMETER ""pma_tx_buf_vod_output_swing_ctrl =31 " -to tx_serial_pin[0]
The following table lists the important transceiver PMA settings but you can obtain a complete list from the “Analog PMA Settings” tab of the Stratix 10 L-Tile/H-Tile Native PHY IP by checking the “Provide sample QSF assignments” option and pasting these into your project QSF file
Table 1: Transmitter PMA Attributes
Attribute | Full Attribute Name | Attribute Values |
TX Output Swing Level (VOD) | pma_tx_buf_vod_output_swing_ctrl | 17-31 (600mV - VCCT or Transmitter Power Supply Voltage) |
Pre-emphasis 1st post-tap magnitude | pma_tx_buf_pre_emp_switching_ctrl_1st_post_tap | 0-24 |
Pre-emphasis 1st post-tap polarity | pma_tx_buf_pre_emp_sign_1st_post_tap | fir_post_1t_neg (negative) OR fir_post_1t_pos (positive) |
Pre-emphasis 1st pre-tap magnitude | pma_tx_buf_pre_emp_switching_ctrl_pre_tap_1t | 0-15 |
Pre-emphasis 1st pre-tap polarity | pma_tx_buf_pre_emp_sign_pre_tap_1t | fir_pre_1t_neg (negative) OR fir_pre_1t_pos (positive) |
Slew Rate | pma_tx_buf_slew_rate_ctrl | slew_r0 slew_r1 slew_r2 slew_r3 slew_r4 slew_r5 |
Table 2: Receiver PMA Attributes
Attribute | Full Attribute Name | Attribute Values |
Equalization Bandwidth | pma_rx_buf_eq_bw_sel | eq_bw_0 (Datarate <= 6.5 Gbps), eq_bw_1 (6.5 Gbps < Datarate <=12.5Gbps), eq_bw_2 (12.5Gbps < Datarate <=19.2Gbps), OR eq_bw_3 (19.2 < Datarate) |
Manual CTLE AC Gain value | pma_rx_buf_ctle_ac_gain | 0-15 |
Manual CTLE EQ Gain value | pma_rx_buf_ctle_eq_gain | 0-47 |
Manual VGA value | pma_rx_buf_vga_dc_gain | 0-31 |
The attribute names have additional prefixes compared to the ones listed in the Register Map of Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide.
This information will be added to a future version of the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide.
