Article ID: 000074004 Content Type: Troubleshooting Last Reviewed: 04/21/2023

Why is flashsm_reset reported as an unconstrained clock in the PFL IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • MicroBlaster™ Fast Passive Parallel Software Driver
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a limitation in the Quartus® Prime software, you may see flashsm_reset reported as an unconstrained clock. This occurs when you instantiate the Parallel Flash Loader (PFL) IP in a MAX® 10 device.

     

     

    Resolution

    Flashsm_reset is not a clock, so it is safe to ignore this warning.

    This problem was fixed in Intel® Quartus® software version 19.1

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs