Description
Due to the nature of the DCFIFO IP in Intel® Stratix® 10 device, wrong data might be observed at the show-ahead output or the first read operation after resetting by aclr. This symptom is only observed when a racing condition occurs between the aclr deassertion and the rdclk rising edge.
Resolution
Use Add circuit to synchronize 'aclr' input with 'rdclk' option from the FIFO parameter editor, or set the READ_ACLR_SYNCH parameter to ON.
See also FIFO Synchronous Clear and Asynchronous Clear Effect of Intel® Stratix® 10 Embedded Memory User Guide version 2020.11.13 and later.