Due to a problem in the Quartus® II software version 12.1 and later, you may see this error in Cyclone® V devices when using the ALTLVDS_TX mega function in external PLL mode.
Error: IR FIFO USERDES Block node 'lvds_tx:lvds_tx_inst0|altlvds_tx:ALTLVDS_TX_component|lvds_tx_lvds_tx:auto_generated|lvds_outclk_tx_serialiser' is not properly connected on the 'LOADEN' port. It must be connected to one of the valid ports listed below.Info: Can be connected to LOADEN port of arriav_pll_lvds_output WYSIWYGInfo: Can be connected to LOADEN port of cyclonev_pll_lvds_output WYSIWYGInfo: Can be connected to OUTCLK port of generic_pll WYSIWYGInfo: Can be connected to OUTCLK port of arriav_clkena WYSIWYG
To workaround this problem, an LVDS buffer needs to be inserted between the external pll and the ALTLVDS instance on the tx_inclock and the tx_enable ports.
Refer to the related solution below to learn how you can add an intermediate LVDS buffer between the external PLL and ALTLVDS IP.