Article ID: 000075391 Content Type: Install & Setup Last Reviewed: 06/09/2017

Why does elaboration of the JESD204B IP Nios control design example fail, with a setting of L=1?


  • Intel® Quartus® Prime Standard Edition
  • JESD204B Intel® FPGA IP

    Elaboration of an Arria® 10 JESD204B Nios control design example with L=1 may fail in Quartus® Prime Standard version 17.0 due to a problem with the Qsys interconnect with the reconfig_* interface, resulting in Qsys not generating the source code files.

    Other JESD204B IP design example variants, including Nios control with L>1, RTL state machine control, generic Nios control, and generic RTL state machine control are not affected by this problem.


    To work around this problem, locate and backup a copy of the following TCL file in your Quartus Prime installation directory:


    • Open the TCL file with text editor. Search for procedure xseries_avmm_adapter.

    • Add $d_L == 1 OR condition check into the if statement below in the xseries_avmm_adapter procedure. There will be 3 occurrences of the if statements in the procedure:

    Before Change :

    if {[param_is_true RECONFIG_SHARED]

    After change :

    if {[param_is_true RECONFIG_SHARED || $d_L == 1}

    • Save the modified TCL file.

    • Re-launch the Quartus Prime software, create a new project or re-open an existing project, and generate the Arria 10 JESD204B design example.

    This problem is scheduled to be fixed in a future version of the Quartus Prime software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs