Article ID: 000075569 Content Type: Product Information & Documentation Last Reviewed: 08/03/2023

How do I address hold time violations for paths where the destination register is implemented inside a dedicated DSP block in Arria® V devices?

Environment

  • Quartus® II Software
  • DSP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 13.1 and earlier, you may see hold violations in Arria® V designs for paths where the source register is implemented using a standard core register and the destination register is implemented as a dedicated DSP input register.

     

     

    Resolution

    To work around this problem, overconstrain the hold requirements during the fitting process by adding this constraint to your Synopsys Design Constraints (.sdc) file:

    if {($::quartus(nameofexecutable) == "quartus_map") || ($::quartus(nameofexecutable) == "quartus_fit")} {
    set_min_delay -from [get_keepers {<sourece register>}] -to [get_keepers {<destination register>}] 0.1
    }

    If the violations you are seeing are greater than 100 ps, then the over-constraint value can be increased.

    This issue has been fixed starting Quartus® II software version 13.1.2

    Related Products

    This article applies to 4 products

    Arria® V GX FPGA
    Arria® V GT FPGA
    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA