When you instantiate the Stratix® IV GX transceiver in PCI Express (PIPE) x8 configuration, the ALTGX MegaWizard® Plug-in Manager provides two bits for the
coreclkout output port, one for each transceiver block.
Altera has identified that during functional simulation of the above configuration, the
coreclkout is always stuck at logic zero. The expected behavior is to have transitions on both
Workaround: Altera recommends that you use only the
coreclkout port to clock the user logic in your design.