For external memory interfaces targeting the hard memory interface resources of Arria V or Cyclone V devices, if you specify an invalid Auto Power Down Cycles value of 51 or greater, an error message appears but does not advise you of the legal range of values. Also, you will not be able to generate your design.
This issue affects UniPHY-based DDR2 and DDR3 interfaces targeting Arria V or Cyclone V devices, with the Enable Hard Memory Interface parameter turned on.
This issue will be fixed in a future version of the DDR2 and DDR3 SDRAM Controller with UniPHY.
This issue has no workaround.