Article ID: 000076231 Content Type: Product Information & Documentation Last Reviewed: 07/29/2013

How does the PLL Usage Summary report the output clock phases for Stratix V, Arria V, and Cyclone V devices using the Altera_PLL megafunction?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The PLL Usage Summary report displays the output clock phases for Stratix® V, Arria® V, and Cyclone® V devices based on the initial counter and VCO tap settings.  The initial counter sets the "coarse" phase shift of the output clock, which is equal to one VCO period.  The VCO tap sets the "fine" phase shift of the output clock, which is equal to 1/8th the VCO period.  Together, these settings give high resolution phase adjustment to the output clocks.

The PLL Usage Summary report lists the initial counter setting as C_Counter_PRST. Valid values are any positive integer value beginning with 1. The VCO phase tap setting is listed as C_Counter_PH_Mux_PRST. Valid values are 0 through 7.

To translate these values to a phase shift in time units, use the following equation:

phase shift = [(C_Counter_PRST - 1) (C_Counter_PH_Mux_PRST / 8)] * VCO_period

The VCO_period is shown in the PLL Usage Summary report as PLL_Output_Clock_Frequency and can be calculated as follows:

VCO_period = Reference_Clock_Frequency * M_Counter / N_Counter

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This article applies to 15 products

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