Article ID: 000076272 Content Type: Troubleshooting Last Reviewed: 08/14/2013

Why does my PCI Express Gen3 simulation down train to x1 link width?

Environment

  • Quartus® II Subscription Edition
  • Simulation
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a known issue, the PCIe® link downtrains to Gen3x1 when simulating  Arria® V GZ or Stratix® V devices using the Altera® bus functional models (BFM).
    Resolution

    As a workaround for simulation only, disable "Enable adaptive equalization (AEQ) block" option within the Transceiver Reconfiguration Controller Megafunction. 

    Related Products

    This article applies to 4 products

    Arria® V GZ FPGA
    Stratix® V GS FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA

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