Article ID: 000076291 Content Type: Error Messages Last Reviewed: 06/25/2020

Warning(16817): Verilog HDL warning at iopll.v(30): overwriting previous definition of iopll module

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the eSRAM Intel® FPGA IP in the Intel Quartus® Prime Pro software versions 19.3 and earlier, if your project is using two eSRAMs, you will see this warning message after analysis and synthesis :

    Warning(16817): Verilog HDL warning at iopll.v(30): overwriting previous definition of iopll module

     

    If the two eSRAMs have the same PLL parameters (PLL reference clock frequency and PLL desired clock frequency), the warning message can be ignored.

    If the two eSRAMs have different PLL parameters, after compilation they will be set to the same PLL frequencies taken from one of the eSRAM IP parameters. Refer to the Quartus Fitter report > Plan Stage > PLL Usage Summary to observe the implemented eSRAM I/O PLL frequencies.

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA