Article ID: 000076418 Content Type: Troubleshooting Last Reviewed: 10/31/2023

Why do several IP design examples fail on the Intel Agilex® 7 FPGA-Series Transceiver SoC Development Kit?

Environment

  • Intel® Quartus® Prime Pro Edition
  • SerialLite
  • Ethernet
  • Intel® CPRI
  • Interlaken (2nd Generation) Intel® FPGA IP
  • JESD204B Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The following Intel® FPGA IP Cores generate example designs for the Intel Agilex® 7 FPGA-Series Transceiver SoC Development Kit with incorrect VID settings.

    1) Serial Lite IV Intel® FPGA IP

    2) Interlaken (2nd Generation) Intel® FPGA IP

    3) Triple-Speed Ethernet Intel® FPGA IP

    4) E-Tile Dynamic Reconfiguration Intel® FPGA IP

    5) E-Tile Hard IP for Ethernet and CPRI PHY Intel® FPGA IP

    6) JESD204B Intel® FPGA IP

    7) JESD204C Intel® FPGA IP

    8) Ethernet Subsystem Intel® FPGA IP

     

     

    Resolution

    The correct VID settings can be found in section 6.1 Add SmartVID settings in the Intel® Quartus® Prime QSF file of the Intel Agilex® F-Series Transceiver-SoC Development Kit User Guide.

    Update the design examples with the correct VID settings as shown below:

    set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ"
    set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 42
    set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
    set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
    set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
    set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
    set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
    set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
    set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00

    set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
    set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
    set_global_assignment -name USE_CONF_DONE SDM_IO16
    set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"

    set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
    set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13"
    set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series