Article ID: 000076580 Content Type: Troubleshooting Last Reviewed: 09/12/2023

Why does the RAM:2-PORT IP fail to generate when using Emulate TDP dual clock mode?

Environment

  • Intel® Quartus® Prime Pro Edition
  • RAM 2-PORT Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Edition software version 20.2 and earlier,  you may see "Error: ram_2port_0.dcfifo_in: "How deep should the FIFO be?" (GUI_Depth) xxx is out of range" when using Emulate TDP dual clock mode of the RAM:2-PORT IP.

    This is because the value of "How many words of memory" in Tab Widths/Blk Type is out of range. It can only be set as 2^n (1<n<18) when using Emulate TDP dual clock mode. 

    Resolution

    No workaround is needed. Set a correct value for the number of words of memory in the Tab Widths/Blk Type, 2^n (1<n<18) when using Emulate TDP dual clock mode.

    Future versions of the Intel® Quartus® Prime Pro Edition Software are scheduled to be enhanced to generate an error message in IP GUI when the value of words of memory is out of range.

    Related Products

    This article applies to 2 products

    Intel Agilex® 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs