When simulating your PCI Express® core you may observe that the PCI Express core appears to come out of reset properly and begin Link Initialization, but does not complete Link Initialization and the tx_out[n] port appears to be continuously in the HiZ state.
This may be the result of your testbench configuration, specifically the configuration of the test_in bus to speed up serial simulation.
To workaround this issue, configure your testbench to speed up link initialization, by setting test_in = 1.
For simulation, it is recommended that you set test_in[39:0] = 0x0AD or 0x0A9.
The meaning of these bits are as listed below:
 = Disable power management
 = Disable the core from entering Compliance Mode
 = FPGA mode
 = Disable scrambling
 = Speed up serial simulation