Article ID: 000076748 Content Type: Error Messages Last Reviewed: 02/11/2023

Warning (15064): PLL output port clk[0] feeds output pin "c0~output" via non-dedicated routing

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see this warning in Intel® Quartus® Prime Software when you have assigned a single-ended dedicated clock output to the n-pin of a differential pin pair in Intel MAX® 10 devices.

 

 

Resolution

For a single-ended dedicated clock output, assign the pin to PLL#_CLKOUTp.

For a differential dedicated clock output, assign the pin pair to PLL#_CLKOUTp and PLL#_CLKOUTn.

Related Products

This article applies to 1 products

Intel® MAX® 10 FPGAs