Due to a known problem in the Intel® Quartus® Prime Pro software versions 19.1 to 19.4, the JESD204B Intel® FPGA IP Example Design may fail to operate correctly when using the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. This is due to 2 missing ports if synthesising and 1 missing port if simulating the JESD204B Intel® FPGA IP Example Design.
To work around this problem, follow the steps below:
1. For example design synthesis, add these two ports into "altera_jesd204_ed_RX_TX.sv" located at "//ed_synth" at line 365.
2. For example design simulation, add this port at line 364 into "altera_jesd204_ed_RX_TX.sv" located at "//ed_sim/testbench/models" at line 365.
This problem is fixed starting from the Intel® Quartus® Prime Pro Edition software version 20.1.