Article ID: 000077155 Content Type: Troubleshooting Last Reviewed: 04/14/2023

Why does an M20K memory incorrectly show error status on the eccstatus port when the initial content data is read out?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 14.0 and earlier, an M20K memory might incorrectly show error status on the eccstatus port when the M20K is used as 2-port RAM with the following two options and the initial content data is read out in Stratix® V FPGAs.

    • Enable error correction code (ECC) to check and correct single-bit errors, double adjacent bit errors and detect triple adjacent bit errors in the Clks/Rd,Byte En tab
    • Yes, use this file for the memory content data in the Mem Init tab

    The error is shown only when the initial content data is read.  After the initial content data is overridden with new data by the write operation, the eccstatus port outputs the correct status for the new data.

    Resolution

    To work around this problem, use 512 words of memory depth regardless of your target memory depth.  Note that if your target memory depth is smaller than 512 words, you need to connect the extra MSB inputs of the write and read address to dummy logic to avoid them being synthesized away. 

    To fix this problem, download and install Patch 4.50 for the Quartus® II software version 13.1.4 from the following links.

    This problem is fixed beginning with the Quartus II software version 14.1.

     

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs