Article ID: 000077425 Content Type: Troubleshooting Last Reviewed: 01/05/2017

Why does the Stratix 10 Native PHY IP Core for PIPE lane polarity inversion not take effect immediately?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When pipe_rx_polarity is asserted to invert the lane polarity, it may take up to 24 PCLKs rather than up to 20 PCLKs in Gen1/2 for the inverted data to appear on the rx_parallel_data bus.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs