Article ID: 000077581 Content Type: Troubleshooting Last Reviewed: 10/21/2011

Reconfiguration of a clock multiplier unit (CMU) PLL in an ALTGX megafunction might fail for Stratix IV GX

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In an ALTGX megafunction, reconfiguration of a clock multiplier unit (CMU) PLL might fail if the CMU PLL drives a transmitter channel using a central clock divider through X4/XN and either

    • The transceiver channel is in bonded mode configuration, or
    • The Use central clock divider to drive the transmitter channels using X4/XN lines option on the Main PLL page of the Reconfiguration Settings tab is on.
    Resolution

    Set location assignments to place the CMU PLL that drives a transceiver channel using a central clock divider at location CMU0 PLL.

    Related Products

    This article applies to 1 products

    Stratix® IV FPGAs