Article ID: 000077763 Content Type: Troubleshooting Last Reviewed: 06/22/2023

Why do I see non-intuitive serial loopback behavior when using the Intel® Quartus® Prime Software Transceiver Toolkit with Intel® Stratix® 10 and Intel Agilex® 7 FPGA E-Tile devices?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see non-intuitive serial loopback behavior using the Intel® Quartus® Prime Software Transceiver Toolkit with Intel® Stratix® 10 and Intel Agilex® 7 E-Tile devices if you have not run any kind of RX Adaptation.

    It is mandatory to run RX Adaptation when using Intel Stratix 10 and Intel Agilex® 7 FPGA E-Tile transceivers. If you have not run RX Adaptation, you may see the following behaviors:

    • The toolkit shows 0 Bit Error Rate (BER) irrespective of internal or external serial loopback
    • 0 BER errors are seen when implementing internal and external loopback on your system  and switching internal serial loopback on and off without halting traffic
    Resolution

    To work around this problem, you must always run RX Adaptation on your Intel Stratix 10 and Intel Agilex® 7 FPGA E-Tile transceivers. A flow for initializing your E-Tile transceivers in the Intel Quartus Prime Software Transceiver Toolkit is documented in the following article:

    https://www.intel.com/content/www/us/en/support/programmable/articles/000077764.html

     

     

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel Agilex® 7 FPGAs and SoC FPGAs