According to the 100G Interlaken MegaCore Function
User Guide, user logic should drive the
signal to an Arria 10 100G Interlaken IP core with the logical AND
pll_locked output signals of the Arria 10 TX
PLL IP cores. However, this information is incomplete. The input
signals to the logical AND should also include the inverse of each
For illustration in the case of a single external TX PLL, refer to Figure 5-3, Arria 10 PLL to Arria 10 100G Interlaken MegaCore Function Connection Diagram, in the "Migrating 100G Interlaken IP Core from Stratix V to Arria 10 Devices" chapter of the Arria 10 Migration Guide.
This issue has no workaround. Ensure you connect the Arria 10 external TX PLLs to your 100G Interlaken IP core according to the instructions in this erratum.
This issue is fixed in version 14.1 of the 100G Interlaken MegaCore Function User Guide.