Article ID: 000077905 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I get recovery/removal timing violations in my RLDRAM II controller design?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

If you constrain the RLDRAM II design using DDR Timing Wizard (DTW) in Quartus® II software version 8.1, you will see recovery/removal timing violations. However, these are false paths that are not correctly constrained. To set the false path assignments, add the following lines to the bottom of the DTW-generated SDC file and rerun TimeQuest Timing Analyzer.

set_false_path -from [get_clocks {dtw_read_<memory_clock_name>*}] -to [get_clocks {g_stratixii_pll_rldramii_pll_inst|altpll_component|pll|clk[0]}]

set_false_path -from [get_clocks {g_stratixii_pll_rldramii_pll_inst|altpll_component|pll|clk[0]}] -to [get_clocks {dtw_read__<memory_clock_name>*}]

Related Products

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Stratix® II FPGAs